makaut-cs-303-computer organization

0

Asked: February 23, 2021In: MAKAUT

11. Write short notes on any three of the following :

0

a) Magnetic recording b) Cache replacement policies c) Non-restoring division method d) Addressing modes e) Booth’s algorithm.

0

Sayani saha

Asked: February 23, 2021In: MAKAUT

10(b). Differentiate between memory and mapped I/O and I/O mapped I/O.

0

0

Sayani saha

Asked: February 23, 2021In: MAKAUT

10. a) Given the following determine the size of the sub-fields in the address for direct mapping, associative mapping and set-associative mapping cache schemes :

0

Main memory 512 MB Cache memory size 1 MB Address space of processor 512 MB Block size ...

0

Sayani saha

Asked: February 23, 2021In: MAKAUT

9(c). Evaluate the arithmetic statement X = ( A * B ) / (C + D ) in one, two and three address machines.

0

0

Sayani saha

Asked: February 23, 2021In: MAKAUT

9(b). Explain the basic DMA operations for transfer of data between memory and Peripherals.

0

0

Sayani saha

Asked: February 23, 2021In: MAKAUT

9(a). What is instruction cycle ? Draw the time diagram for memory write operation.

0

0

Sayani saha

Asked: February 23, 2021In: MAKAUT

8(d). Define : (i) rotational latency, (ii) seek time.

0

0

Sayani saha

Asked: February 23, 2021In: MAKAUT

8(c). A three level memory system having cache access time of 5 nsec and disk access time of 40 nsec, has a cache hit ratio of 0.96 and main memory hit ratio of 0.9. What should be the main memory access time to achieve an overall access time of 16 nsec ?

0

0

Sayani saha

Asked: February 23, 2021In: MAKAUT

8(b). What is cache memory ? How does it increase the performance of a computer ? What is hit ratio ?

0

0

Sayani saha

Asked: February 23, 2021In: MAKAUT

8(a). Draw the internal cell diagram of PROM and explain its functionality ?

0

11. Write short notes on any three of the following :

10(b). Differentiate between memory and mapped I/O and I/O mapped I/O.

10. a) Given the following determine the size of the sub-fields in the address for direct mapping, associative mapping and set-associative mapping cache schemes :

9(c). Evaluate the arithmetic statement X = ( A * B ) / (C + D ) in one, two and three address machines.

9(b). Explain the basic DMA operations for transfer of data between memory and Peripherals.

9(a). What is instruction cycle ? Draw the time diagram for memory write operation.

8(d). Define : (i) rotational latency, (ii) seek time.

8(c). A three level memory system having cache access time of 5 nsec and disk access time of 40 nsec, has a cache hit ratio of 0.96 and main memory hit ratio of 0.9. What should be the main memory access time to achieve an overall access time of 16 nsec ?

8(b). What is cache memory ? How does it increase the performance of a computer ? What is hit ratio ?

8(a). Draw the internal cell diagram of PROM and explain its functionality ?

Questions Categories

MAKAUT

NCERT 11th Maths

NCERT 10th Maths

NCERT 12th Maths

Advance Management of Data(AMD)

Python

Technology

R

Sign Up

Sign In

Forgot Password

eduhilfe Latest Questions

Questions Categories