i) one stable state ii) two table states iii) no stable state iv) none of these.
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Sayani saha
Asked: April 12, 2021In: MAKAUT
i) 3 ii) 4 iii) 5 iv) 6.
Sayani saha
Asked: April 12, 2021In: MAKAUT
i) 1 ii) n iii) 2n+1 iv) n+1 clock pulse/pulses.
i) TTL ii) CMOS iii) RTL iv) ECL.
i) a half adder & an OR gate ii) a half adder & an AND gate iii) two half adders & an OR gate iv) none of these.
a) AVL Tree b) Tail Recursion c) collision Resolution using chaining d) Dequeue- operation & application e) Warshall’s Algorithm.