i) 1 ii) n iii) 2n+1 iv) n+1 clock pulse/pulses.
eduhilfe Latest Questions
i) TTL ii) CMOS iii) RTL iv) ECL.
i) a half adder & an OR gate ii) a half adder & an AND gate iii) two half adders & an OR gate iv) none of these.
a) ERROM b) PLD c) A/D converter d) Johnson counter.
i) the ideal scale factor in V/step ii) the analog o/p corresponding to the binary i/p 0110. iii) resolution in % iv) full scale o/p v) the maximum deviation in volts from the best display straight line in order to meet standard linearity.
a) propagation delay b) fan-in c) fan-out d) power dissipation e) floating outputs.
F= m ( 0, 2, 3, 6, 8, 9, 12, 14).
F(W, X, Y, Z)= m( 0, 4, 5, 6, 8, 9 )+ d( 10, ...
a) any even number of error b) any odd number of error c) both (a) and (b) d) none of these.
a) J-K flip-flop b) D flip-flop c) T flip-flop d) None of these.
a) majority logic b) minority logic c) XOR logic d) NAND logic.
a) decoder b) multiplexer c) encoder d) de Multiplexer.
a) 2 MHz b) 1.5MHz c) 50MHz d) 25 KHz.
a) 0.62% b) 0.38% c) 0.39% d) 1.25%.
a) Encoder b) Parity generator c) Multiplexer d) Demultiplexer.